1. Field of the Invention
The present invention relates to a capacitor of a semiconductor device and a manufacturing method thereof. More particularly, the present invention relates to a capacitor of a semiconductor device and a method of manufacturing the capacitor of the semiconductor device, which can crystallize a dielectric layer of the capacitor of the semiconductor device even at low temperatures by forming the dielectric layer of a niobium (Nb)-based tantalum oxide layer, thereby improving the performance of the semiconductor device.
2. Description of the Related Art
Due to the sophistication of semiconductor processes, an integration density of semiconductor integrated circuits and an operating speed of semiconductor devices equipped with such semiconductor integrated circuits have dramatically increased. Various methods of increasing the storage capacity of a semiconductor memory device having a capacitor, such as dynamic random access memory (DRAM), while reducing the size of the semiconductor memory device, have been extensively researched. In addition, in order to provide at least minimally required effective capacitance while increasing the integration density of semiconductor devices, various shapes of capacitors, e.g., stack-type, cylindrical, and pin-type capacitors, have been developed. Moreover, various efforts also have been made to decrease a thickness-of-oxide (Tox) of semiconductor devices for data storage, such as DRAMs, even when high dielectric materials are used for increasing the integration density of semiconductor devices.
FIG. 1 illustrates a cross-sectional view of a conventional semiconductor device having a capacitor formed of a high dielectric material. Referring to FIG. 1, the semiconductor device includes a semiconductor substrate 11, e.g., a silicon substrate, and a polysilicon layer 12 formed on the semiconductor substrate 11. In a capacitor of the conventional semiconductor device, a lower electrode layer, a dielectric layer 15, and an upper electrode layer 16 are sequentially stacked on the polysilicon layer 12. The lower electrode layer is formed of a double layer of a titanium nitride (TiN) layer 13 and a ruthenium (Ru) layer 14. Here, the TiN layer 13 serves as a barrier layer for preventing impurities from the substrate 11 from diffusing into upper layers. The dielectric layer is formed of a tantalum oxide (Ta2O5) layer 15. The upper electrode layer 16 is formed on the Ta2O5 layer 15.
A typical DRAM can be formed by coating Ta2O5, which is a high dielectric material, on the substrate 11 using a chemical vapor deposition (CVD) or atomic layer deposition (ALD) method. The Ta2O5 layer is crystallized so that it can have electrical characteristics. In order to provide the Ta2O5 layer 15 with electrical characteristics, it is necessary to crystallize the Ta2O5 layer 15 by performing a heat treatment process on the Ta2O5 layer 15 at a temperature of about 700° C. or higher. During the heat-treatment of the Ta2O5 layer 15, however, oxygen radicals contained in the Ru layer 14 may diffuse into the lower TiN layer 13, which is below the Ru layer 14. Resultantly, the TiN layer 13 may be undesirably oxidized or deformed. In order to prevent the oxidization or deformation of the TiN layer 13, the Ta2O5 layer 15 should be heat-treated at a low temperature. Disadvantageously, when the heat treatment is performed at a low temperature, the Ta2O5 layer 15 may not be crystallized, thereby deteriorating the electrical characteristics of the Ta2O5 layer 15.